Operating point & validation calculated model
Duty ratio D (non-ideal)—
Inductor average current—
LC natural frequency f0—
RHP zero / ESR zero—
Enter parameters and recalculate.
Operating point equations will appear here.
State-space matrices will appear here.
Small-Signal Modeling & Loop Design Guidelines:
• Capacitor ESR Zero: ωesr = 1/(C·Rc) introduces +90° phase lead at high frequency.
• Inductor ESR Rl & Cap ESR Rc: Increases damping (lowers Q) of the LC complex pole pair.
• RHP Zero (Boost / Buck-Boost): Limits closed-loop bandwidth fc < fRHP / 5.
• Phase Margin vs. Peak Overshoot: PM = 45° → 16% overshoot | PM = 60° → 4.6% overshoot (optimal) | PM = 30° → 37% overshoot.
• Capacitor ESR Zero: ωesr = 1/(C·Rc) introduces +90° phase lead at high frequency.
• Inductor ESR Rl & Cap ESR Rc: Increases damping (lowers Q) of the LC complex pole pair.
• RHP Zero (Boost / Buck-Boost): Limits closed-loop bandwidth fc < fRHP / 5.
• Phase Margin vs. Peak Overshoot: PM = 45° → 16% overshoot | PM = 60° → 4.6% overshoot (optimal) | PM = 30° → 37% overshoot.
Selected plant equation
—
Model assumptions
State-space averaged CCM · includes Inductor ESR (Rl) & Capacitor ESR (Rc) · resistive load R = Vo²/P
Architecture dropdown automatically filters the available plants. In Cascaded mode with Gvi(s) = Vout/IL, the inner current loop is modelled as Ti(s) = ωci/(s+ωci) using the “Inner current-loop BW” input.
Plant margins (unity feedback, uncompensated)
| Plant | Definition | Numerator coefficients (descending s) | Denominator coefficients |
|---|
Calculated crossover—
Phase margin—
Gain margin—
Est. step overshoot—
Calculate a compensator to see closed-loop poles and checks.
Calculate a compensator to view the transfer function.
Calculate a compensator to verify phase and gain margins.
Analog Op-Amp Hardware Realization
Inverting Error Amplifier + Reference Voltage Source Vref + PWM Ramp Comparator (Modulator gain Gm = 1/Vp).
Calculate a compensator to synthesize the analog Op-Amp circuit.
| Component | Role in Compensator | Exact Calculated Value | Standard E96 / E24 Value | Design Formula |
|---|
Continuous controller Gc(s)
—
Discrete controller Gc(z) & Difference Equation
Click “Discretize controller”.
Discrete stability must be evaluated with the sampled plant, ZOH, actual PWM update timing and delays.
Generate C source after calculating and discretizing a controller.
Design provenance and modeling checklist
✓ Non-ideal CCM state-space matrices with Rl (DCR) and Rc (ESR)
✓ Architecture-based plant filtering (VMC, ACMC, and Cascaded Voltage+Current)
✓ Cascaded Vout/IL closed-loop response models the inner current loop as Ti(s)=ωci/(s+ωci) and includes ZOH + computation delay to evaluate Vout/Vref
✓ Op-Amp hardware realization with E96/E24 component sizing and vertical Zf(s)/Zin(s) transfer functions
✓ Phase Margin to transient overshoot mapping
✓ Selected-compensator pointer-driven C engine shared across 4 loops (Buck V/I & Boost V/I)
Reference library supplied for this project
- Switched Mode Power Conversion, Dept. of Electrical Engineering, IISc Bangalore: Steady-State & Non-Idealities, State-Space Averaging with Rl & Rc, Closed-Loop Control, Op-Amp Realisation, and Current Programmed Control.
- TI, Practical Feedback Loop Analysis for Voltage-Mode Boost Converter, SLVA633 (2014).
- Cao, Type III Compensator Design for Power Converters.
Exportable report
Engineering limits — read before using results
This platform implements small-signal state-space averaged CCM models including inductor ESR (Rl) and capacitor ESR (Rc), K-factor exact phase-margin synthesis, analog Op-Amp circuit synthesis, and pointer-driven 4-loop C-code generation for the selected compensator structure. Always verify switching ripple stability, slope compensation (if peak current mode), op-amp gain-bandwidth product (GBWP > 20× fp2), and hardware protections before powering prototypes.